1. Field of the Invention
The present invention generally relates to VLIW DSPs (very long instruction word digital signal processor), and methods for operating the same. More specifically, the present invention is directed to improvement in binary translation for VLIW DSPs.
2. Description of the Related Art
The VLIW architecture is known as one of the promising DSP architectures due to the higher performance with simple hardware implementations. One feature of VLIW architectures is that each instruction includes multiple sub-instructions; VLIW architectures specify multiple operations (such as load, store, arithmetic processing, and branching) per instruction. This allows VLIW DSPs to perform highly efficient parallel processing, and to thereby provide high-speed data processing. A recent trend is to increase the degree of parallelism (that is, the number of sub instructions within a single VLIW instruction) for achieving higher data processing speed. Japanese Open Laid Patent Application No. Jp-A-Heisei 7-234792 discloses a technique for generating program codes with increased degree of parallelism.
Binary translation, which designates a technique for allowing specific software adapted to a certain DSP to be executable on other DSPs, is one of the important aspects in the development of VLIW DSPs. It is not preferable to newly develop software for a newly developed DSP, in view of the reduction in the cost and the TAT (turn around time). A next-generation DSP is preferably adapted to execute software designed for the old-generation DSPs.
The binary translation technique may constitute an important aspect, especially in DSPs for real-time signal processing in multi-task situation, for example, DSPs for simultaneously performing audio and video data processing operations. Such DSPs require sophisticated programming techniques to achieve high execution efficiency. Therefore, hand assembling (namely, manual programming with an assembly language or a machine language) is often used to develop software in place of high-level language programming, such as C language programming. The use of hand assembling, however, undesirably requires increased man-hours for developing DSP software. It would be advantageous if DSPs requiring hand-assembled programs are adapted to binary translation.
Two sorts of techniques are known as binary translation: one is static binary translation, and the other is dynamic binary translation. Static binary translation involves translating codes within a program off line before the program is executed. Dynamic binary translation, on the other hand, involves translating codes within a program during executing the program within the DSP.
Japanese Open Laid Patent Application No. 2003-140910A discloses a dynamic binary translation technique. This conventional-dynamic binary translation technique addresses avoiding a conflict over a hardware resource within a VLIW processor which requires avoiding resource conflict between instructions using software. In the conventional dynamic binary translation technique, a processor is designed to detect recourse conflicts, and provided with a resource conflict check register indicating the occurrence of resource conflicts. When performing dynamic binary translation, the processor checks whether or not a resource conflict occurs through actually executing codes. This effectively reduces processing time required for instruction scheduling in dynamic binary translation.
One of the issues in binary translation for DSPs is that a VLIW DSP adapted to a program having an enhanced degree of parallelism does not exhibit its intrinsic superior performance, when executing a program having a reduced degree of parallelism. An improvement in the processing speed cannot be expected when a program adapted to a VLIW DSP having a reduced degree of parallelism is executed on another VLIW DSP having an enhanced degree of parallelism, because of a reduced number of sub-instructions per instruction. Let us consider a case, for instance, where a pair of programs “A” and “B” adapted to a VLIW DSP having a reduced degree of parallelism. Even when the programs “A” and “B” are executed by such a VLIW DSP having an enhance degree of parallelism, the execution speed is restricted due to the reduced number of sub instructions per instruction within the programs “A” and “B”; the improvement in the execution speed is not achieved by the enhancement in the degree of parallelism of the VLIW DSP hardware.
There is a need for providing a binary translation technique for achieving high-speed operation through making use of the performance of a highly parallelized VLIW DSP even in the case where a program adapted to a VLIW DSP having a reduced degree of parallelism is executed on the highly parallelized VLIW DSP.